IC Package Layout Design Engineer (Contract)

Ayar Labs
Ayar Labs

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Marketing & Communications, Product, Design

hsinchu, east district, hsinchu city, taiwan

Posted on Apr 8, 2026
Position: IC Package Layout Design Engineer (Contract)
Location: Hsinchu, Taiwan
Job Id: 565
# of Openings: 0
IC Package Layout Design Engineer
Location: Taiwan
Job Type: 1 Year Contract
Team: Packaging Engineering – Ayar Labs
About Ayar Labs
Ayar Labs is pioneering the future of computing with our optical I/O technology, enabling dramatically higher bandwidth, lower latency, and improved power efficiency compared to traditional electrical interconnects. Our innovations in silicon photonics and advanced packaging are redefining system architectures for AI, HPC, cloud, and defense applications.
We are seeking a talented IC Package Layout Design Engineer to join our packaging team. This engineer will be responsible for developing advanced package layouts for electro-optical ICs while ensuring high performance, manufacturability, and reliability.
Responsibilities
  • Own and execute package substrate layout design for flip-chip, 2.5D/3D, and heterogeneous integration packages.
  • Define and optimize ball map, stack-up, power/ground distribution, and high-speed signal routing.
  • Work closely with silicon, optical, and system design teams to translate requirements into robust layout implementations.
  • Support signal integrity (SI) and power integrity (PI) analysis through accurate layout modeling and extraction.
  • Perform DRC, LVS, and ERC checks to ensure design quality and manufacturability.
  • Collaborate with OSATs, foundries, and EDA vendors to ensure design for manufacturability (DFM) and yield optimization.
  • Maintain package design libraries, flows, and documentation.
  • Contribute to the development of new packaging approaches to enable optical I/O integration at scale.
Qualifications
Required:
  • B.S. or M.S. in Electrical Engineering, or related field.
  • 5+ years of experience in IC package layout and substrate design.
  • Proficiency with industry-standard EDA tools (Cadence Allegro Package Designer, or equivalent).
  • Solid understanding of high-speed interconnects, power delivery, and signal integrity.
  • Experience with substrate stack-up definition, routing constraints, and package reliability requirements.
  • Strong problem-solving and cross-functional collaboration skills.
Preferred:
  • Experience in heterogeneous integration, chiplet architectures, or silicon photonics packaging.
  • Familiarity with optical/electrical co-design challenges.
  • Knowledge of thermal and mechanical reliability considerations in advanced packaging.
  • Experience collaborating with OSATs and foundries on complex package substrates.
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See open jobs at Ayar Labs.See open jobs similar to "IC Package Layout Design Engineer (Contract)" Insight Partners.
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