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Engineer, ASIC Design

Ayar Labs
Design
San Jose, CA, USA
Posted on Feb 14, 2026
     
  Position: Engineer, ASIC Design  
     Location:   San Jose, CA  
  
  Job Id: 542  
  # of Openings: 0  
    
  Engineer, ASIC Design
 
 Location: San Jose (on-site)
 
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.
 
Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. 

 The ASIC Engineer is responsible for design and integration of complex SoCs with both high-speed custom and digital blocks. You will work in a dynamic startup environment as part of a small IC design team, covering roles from custom circuit design to optical device design. Each team member is expected to contribute across a broad range of tasks and to gain new skill sets to grow with the company. The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.


KEY RESPONSIBILITIES:
Develop and optimize RTL designs for use in complex digital systems
Develop verification methodology and testbenches for digital and mixed-signal blocks 
Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems
Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff 
 
Required Skills:
BS or MS in Electrical Engineering, Computer Engineering, or related fields
1+ years of work or academic experience in ASIC design
History of assuming responsibility for a variety of technical tasks and completing projects independently
Proficient in Verilog for both RTL design and verification
Proficient in ASIC verification (XCelium, VCS, Questa) tools
Proficient in scripting or programming languages
 
 Preferred Skills: 
Proficient in writing timing constraints and deep understanding of timing analysis
Experience working on digital designs with multiple clock domains and clock dividers
Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
Performed silicon bring-up, debug, and evaluation
Programming experience in Python, low-level languages (C, C++)
Some knowledge of optics and control systems
 
Salary Range: $130,000 - $150,000
 
 NOTE TO RECRUITERS:
 Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
 
 Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply. 

 
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