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Engineer, Physical Design

Ayar Labs
Design
San Jose, CA, USA
Posted on Jan 23, 2026
     
  Position: Engineer, Physical Design  
     Location:   San Jose, CA  
  
  Job Id: 532  
  # of Openings: 0  
    
 Physical Design Engineer:
 
Location: San Jose (on-site)
 
We are seeking a collaborative Physical Design Engineer to join our high-performance ASIC/SoC team. In this role, you will contribute to the development of next-generation electro-optical engines and complex mixed-signal designs. You will work alongside technical leads to transform RTL into silicon-ready GDS, gaining exposure to leading-edge process nodes and advanced packaging technologies.
 
 This is a growth-oriented role designed for an engineer with a strong foundation in VLSI who is eager to master the complete physical design flow, from synthesis to signoff.
 
 
Essential Functions
Block-Level Implementation: Execute the full physical design flow (RTL2GDS) for digital and mixed-signal blocks, including floorplanning, power planning, placement, and routing.
Timing Closure: Perform Static Timing Analysis (STA) to identify setup/hold violations and implement ECOs to achieve timing convergence.
Clock Tree Synthesis (CTS): Analyze clock structures and assist in optimizing clock distribution for skew and latency.
Physical Verification: Run and debug DRC, LVS, and Antenna checks using industry-standard verification tools to ensure manufacturing compliance.
Power Optimization: Participate in power optimization, including clock gating, power domain, and IR drop analysis.
Automation: Develop and maintain Tcl/Python scripts to automate standard design tasks and improve flow efficiency.
Cross-Functional Collaboration: Partner with the RTL design and Custom Layout teams to resolve integration issues and ensure clean hand-offs.
 
 Basic Qualifications 
Bachelor’s degree in Electrical/Computer Engineering (or related field) with 2+ years of industry experience in physical design OR Master’s degree in Electrical/Computer Engineering (or related field) with 0-2 years of industry experience.
Strong understanding of digital logic design and CMOS device physics.
Familiarity with the ASIC design cycle, including Synthesis, P&R, STA, and Signoff.
Hands-on experience (via work or academic projects) with industry-standard P&R tools (e.g., Cadence Innovus/Encounter, Synopsys ICC2/Fusion Compiler).
Proficiency in scripting languages (Tcl, Python, or Perl) for design automation and data parsing.
Comfortable working in a Linux/Unix environment.
 
 Preferred Qualifications 
Experience or coursework in Advanced Process Nodes (7nm, 5nm, or smaller).
Prior internship or co-op experience in a Physical Design or Hardware Engineering role.
Familiarity with physical verification tools such as Mentor Calibre or Synopsys IC Validator.
Understanding of low-power design standards (UPF/CPF).
Knowledge of timing constraints (SDC), or signal integrity analysis.
Experience with version control systems (e.g., Git, Perforce, Subversion).
 
 
 Salary range: $120,000 - $160,000
 
 NOTE TO RECRUITERS:
 Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
  
 About Ayar Labs:
  
 At Ayar Labs we’re about to revolutionize computing by moving data with light. We’re unleashing processing power for artificial intelligence, high performance computing, cloud and telecommunications by removing the bottlenecks created by today’s electrical I/O -- making it possible to continue scaling computing system performance. Ayar Labs is the first to deliver an optical I/O solution that combines in-package optical I/O chiplets and multi-wavelength remote light sources to replace traditional electrical I/O. This silicon photonics-based I/O solution enables chips to communicate with each other from millimeters to kilometers, to deliver orders of magnitude improvements in latency, bandwidth density, and power consumption.
 With our strong collaborations with industry leaders and government, our deep ties to MIT and UC Berkeley, and our commitment to hiring the best engineers in photonics and electronics, joining our team gives you the opportunity to collaborate with renowned experts on challenging, paradigm-shifting work.
 We are passionate about delivering in-package optical I/O at scale, leveraging the strength of our patent portfolio and our team of leading interdisciplinary experts. We believe that deep cross-collaboration between teams facilitated by honest, open debate is the best way to drive innovation and achieve big wins. Join our team and experience the possibilities.
 Resources:
 Executives from Intel and GLOBALFOUNDRIES share their thoughts on Ayar Labs and the promise of in-package optical I/O (video)
 Ayar Labs in the News and Recent announcements
  LinkedIn and Twitter 
 
 Ayar Labs is an Affirmative Action/Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply. 

 
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